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An opcode table (also called an opcode matrix) is a visual representation of all opcodes in an instruction set. It is arranged such that each axis of the table represents an upper or lower nibble, which combined form the full byte of the opcode. Additional opcode tables can exist for additional instructions created using an opcode prefix.

• Table values

• Example opcode table

• References

• External links

The structure and arrangement of an opcode table appears as follows:

| | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E |

|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

| 0 | 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | 0A | 0B | 0C | 0D | 0E |

| 1 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 1A | 1B | 1C | 1D | 1E |

| 2 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 2A | 2B | 2C | 2D | 2E |

| 3 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 3A | 3B | 3C | 3D | 3E |

| 4 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 4A | 4B | 4C | 4D | 4E |

| 5 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 5A | 5B | 5C | 5D | 5E |

| 6 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 6A | 6B | 6C | 6D | 6E |

| 7 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 7A | 7B | 7C | 7D | 7E |

| 8 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 8A | 8B | 8C | 8D | 8E |

| 9 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 9A | 9B | 9C | 9D | 9E |

| A | A0 | A1 | A2 | A3 | A4 | A5 | A6 | A7 | A8 | A9 | AA | AB | AC | AD | AE |

| B | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | B8 | B9 | BA | BB | BC | BD | BE |

| C | C0 | C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 | C9 | CA | CB | CC | CD | CE |

| D | D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | DA | DB | DC | DD | DE |

| E | E0 | E1 | E2 | E3 | E4 | E5 | E6 | E7 | E8 | E9 | EA | EB | EC | ED | EE |

| F | F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | FA | FB | FC | FD | FE |

| | F |

|---|---|

| 0 | 0F |

| 1 | 1F |

| 2 | 2F |

| 3 | 3F |

| 4 | 4F |

| 5 | 5F |

| 6 | 6F |

| 7 | 7F |

| 8 | 8F |

| 9 | 9F |

| A | AF |

| B | BF |

| C | CF |

| D | DF |

| E | EF |

| F | FF |

Each cell from 00-FF contains information about the operation such as the equivalent assembly instruction corresponding to the opcode, parameters, and CPU cycle counts.

This is the opcode table for the MOS Technology 6502 microprocessor from 1975. The 6502 uses 8-bit opcodes. Of the 256 possible opcodes available using an 8-bit pattern, the original 6502 uses only 151 of them, organized into 56 instructions with (possibly) multiple addressing modes.cite-ref-ii-1-0[1] Because not all the 256 opcodes are not used, some opcode spaces are blank and the low nibble columns 3, 7, B, and F are missing from the table.

| Opcode matrix for the 6502 instruction… | | | | |

|---|---|---|---|---|

| Addressing modes: A – accumulator, # –… | | | | |

| High nibble | Low nibble | | | |

| High nibble | 0 | 1 | 2 | 4 |

| 0 | BRK | ORA ( ind ,X) | | |

| 1 | BPL rel | ORA ( ind ),Y | | |

| 2 | JSR abs | AND ( ind ,X) | | BIT zpg |

| 3 | BMI rel | AND ( ind ),Y | | |

| 4 | RTI | EOR ( ind ,X) | | |

| 5 | BVC rel | EOR ( ind ),Y | | |

| 6 | RTS | ADC ( ind ,X) | | |

| 7 | BVS rel | ADC ( ind ),Y | | |

| 8 | | STA ( ind ,X) | | STY zpg |

| 9 | BCC rel | STA ( ind ),Y | | STY zpg ,X |

| A | LDY # | LDA ( ind ,X) | LDX # | LDY zpg |

| B | BCS rel | LDA ( ind ),Y | | LDY zpg ,X |

| C | CPY # | CMP ( ind ,X) | | CPY zpg |

| D | BNE rel | CMP ( ind ),Y | | |

| E | CPX # | SBC ( ind ,X) | | CPX zpg |

| F | BEQ rel | SBC ( ind ),Y | | |

| Opcode matrix for the 6502 instruction… | | | | | |

|---|---|---|---|---|---|

| High nibble | 5 | 6 | 8 | 9 | A |

| 0 | ORA zpg | ASL zpg | PHP | ORA # | ASL A |

| 1 | ORA zpg ,X | ASL zpg ,X | CLC | ORA abs ,Y | |

| 2 | AND zpg | ROL zpg | PLP | AND # | ROL A |

| 3 | AND zpg ,X | ROL zpg ,X | SEC | AND abs ,Y | |

| 4 | EOR zpg | LSR zpg | PHA | EOR # | LSR A |

| 5 | EOR zpg ,X | LSR zpg ,X | CLI | EOR abs ,Y | |

| 6 | ADC zpg | ROR zpg | PLA | ADC # | ROR A |

| 7 | ADC zpg ,X | ROR zpg ,X | SEI | ADC abs ,Y | |

| 8 | STA zpg | STX zpg | DEY | | TXA |

| 9 | STA zpg ,X | STX zpg ,Y | TYA | STA abs ,Y | TXS |

| A | LDA zpg | LDX zpg | TAY | LDA # | TAX |

| B | LDA zpg ,X | LDX zpg ,Y | CLV | LDA abs ,Y | TSX |

| C | CMP zpg | DEC zpg | INY | CMP # | DEX |

| D | CMP zpg ,X | DEC zpg ,X | CLD | CMP abs ,Y | |

| E | SBC zpg | INC zpg | INX | SBC # | NOP |

| F | SBC zpg ,X | INC zpg ,X | SED | SBC abs ,Y | |

| Opcode matrix for the 6502 instruction… | | | |

|---|---|---|---|

| High nibble | C | D | E |

| 0 | | ORA abs | ASL abs |

| 1 | | ORA abs ,X | ASL abs ,X |

| 2 | BIT abs | AND abs | ROL abs |

| 3 | | AND abs ,X | ROL abs ,X |

| 4 | JMP abs | EOR abs | LSR abs |

| 5 | | EOR abs ,X | LSR abs ,X |

| 6 | JMP ( ind ) | ADC abs | ROR abs |

| 7 | | ADC abs ,X | ROR abs ,X |

| 8 | STY abs | STA abs | STX abs |

| 9 | | STA abs ,X | |

| A | LDY abs | LDA abs | LDX abs |

| B | LDY abs ,X | LDA abs ,X | LDX abs ,Y |

| C | CPY abs | CMP abs | DEC abs |

| D | | CMP abs ,X | DEC abs ,X |

| E | CPX abs | SBC abs | INC abs |

| F | | SBC abs ,X | INC abs ,X |

cite-note-ii-11. ↑ citerefparkerParker, Neil. "The 6502/65C02/65C816 Instruction Set Decoded". Neil Parker's Apple II page. Archived from the original on 2019-07-16. Retrieved 2019-07-16.

• Game Boy LR35902 opcode table

• Z80 opcode table

• Intel x86 opcode table

• 6502/6510/8500/8502 opcode table